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DFT
2002
IEEE
121views VLSI» more  DFT 2002»
14 years 15 days ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
ICCAD
2000
IEEE
72views Hardware» more  ICCAD 2000»
13 years 12 months ago
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation
The Charge Sharing (CS) problem is one of notorious noise problems in domino circuits design and test. In this paper, this problem is thoroughly investigated by considering circui...
Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen...
ICCAD
1999
IEEE
77views Hardware» more  ICCAD 1999»
13 years 12 months ago
Symbolic functional and timing verification of transistor-level circuits
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
Clayton B. McDonald, Randal E. Bryant
ICCAD
1997
IEEE
131views Hardware» more  ICCAD 1997»
13 years 11 months ago
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits
Maximum instantaneous power in VLSI circuits has a great impact on circuit's reliability and the design of power and ground lines. To synthesizehighlyreliablesystems,accurate...
Chuan-Yu Wang, Kaushik Roy
ICES
2003
Springer
108views Hardware» more  ICES 2003»
14 years 23 days ago
A Morphogenetic Evolutionary System: Phylogenesis of the POEtic Circuit
Abstract. This paper describes a new evolutionary mechanism developed specifically for cellular circuits. Called morphogenetic system, it is inspired by the mechanisms of gene exp...
Daniel Roggen, Dario Floreano, Claudio Mattiussi