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ISPD
1998
ACM
244views Hardware» more  ISPD 1998»
13 years 11 months ago
Analysis, reduction and avoidance of crosstalk on VLSI chips
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
Tilmann Stöhr, Markus Alt, Asmus Hetzel, J&uu...
IJON
2006
189views more  IJON 2006»
13 years 7 months ago
Storing and restoring visual input with collaborative rank coding and associative memory
Associative memory in cortical circuits has been held as a major mechanism for content-addressable memory. Hebbian synapses implement associative memory efficiently when storing s...
Martin Rehn, Friedrich T. Sommer
ICCAD
2009
IEEE
92views Hardware» more  ICCAD 2009»
13 years 5 months ago
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield ra...
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak
ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
14 years 4 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz