605 search results - page 102 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
SBACPAD
2008
IEEE
14 years 2 months ago
2008
IEEE
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
DAC
1999
ACM
14 years 9 months ago
1999
ACM
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
DAC
1996
ACM
14 years 18 days ago
1996
ACM
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
In recent literature it has been reported that Dynamic Power Management (DPM) may lead to decreased reliability in real-time embedded systems. The ever-shrinking device sizes cont...