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DAC
1994
ACM
13 years 11 months ago
Synthesis of Instruction Sets for Pipelined Microprocessors
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
Ing-Jer Huang, Alvin M. Despain
ARC
2006
Springer
157views Hardware» more  ARC 2006»
13 years 11 months ago
PISC: Polymorphic Instruction Set Computers
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...
Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Won...
DAC
1997
ACM
13 years 11 months ago
ISDL: An Instruction Set Description Language for Retargetability
Abstract—We present the Instruction Set Description Language, ISDL, a machine description language used to describe target architectures to a retargetable compiler. The features ...
George Hadjiyiannis, Silvina Hanono, Srinivas Deva...
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
14 years 28 days ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
ASM
2008
ASM
13 years 9 months ago
Using EventB to Create a Virtual Machine Instruction Set Architecture
A Virtual Machine (VM) is a program running on a conventional microprocessor that emulates the binary instruction set, registers, and memory space of an idealized computing machine...
Stephen Wright