171 search results - page 8 / 35 » Sensitivity analysis in decision circuits |
ITC
1996
IEEE
14 years 1 months ago
1996
IEEE
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of IDD switching transients on the supply rails and voltage transients at selected test...
ASPDAC
2007
ACM
14 years 1 months ago
2007
ACM
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
A new method is presented to model symbolically strongly nonlinear circuits, characterized by Piece-Wise Linear (PWL) functions. The method follows the idea of Bokhoven and Leenae...
GECCO
2009
Springer
14 years 1 months ago
2009
Springer
Software engineering is plagued by problems associated with unreliable cost estimates. This paper introduces an approach to sensitivity analysis for requirements engineering. It u...
ICCAD
2008
IEEE
14 years 6 months ago
2008
IEEE
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...