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DAC
2004
ACM
14 years 8 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
14 years 28 days ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
DATE
2010
IEEE
170views Hardware» more  DATE 2010»
14 years 22 days ago
Analytical model for TDDB-based performance degradation in combinational logic
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, R...
TCAD
2010
106views more  TCAD 2010»
13 years 6 months ago
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimo...
ICCAD
2001
IEEE
95views Hardware» more  ICCAD 2001»
14 years 4 months ago
On the Signal Bounding Problem in Timing Analysis
In this paper, we study the propagation of slew dependent bounding signals and the corresponding slew problem in static timing analysis. The selection of slew from the latest arri...
Jin-fuw Lee, Daniel L. Ostapko, Jeffery Soreff, C....