225 search results - page 14 / 45 » Sequential Circuits for Relational Analysis |
ICCAD
2002
IEEE
14 years 6 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
ISCAS
1999
IEEE
14 years 1 months ago
1999
IEEE
Dynamic translinear (DTL) circuits use the exponential inputoutput relation of the transistor as a primitive for the synthesis of electronic circuits. As a consequence the analysi...
ASPDAC
2006
ACM
14 years 3 months ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...
SBCCI
2006
ACM
14 years 3 months ago
2006
ACM
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...