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» Sequential circuits for program analysis
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PPOPP
2012
ACM
12 years 3 months ago
DOJ: dynamically parallelizing object-oriented programs
We present Dynamic Out-of-Order Java (DOJ), a dynamic parallelization approach. In DOJ, a developer annotates code blocks as tasks to decouple these blocks from the parent executi...
Yong Hun Eom, Stephen Yang, James Christopher Jeni...
ICCAD
1997
IEEE
112views Hardware» more  ICCAD 1997»
13 years 12 months ago
Circuit optimization via adjoint Lagrangians
The circuit tuning problem is best approached by means of gradient-based nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the o...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
13 years 11 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
EMSOFT
2004
Springer
13 years 11 months ago
A methodology for generating verified combinatorial circuits
High-level programming languages offer significant expressivity but provide little or no guarantees about resource use. Resourcebounded languages -- such as hardware-description l...
Oleg Kiselyov, Kedar N. Swadi, Walid Taha
FPL
2004
Springer
94views Hardware» more  FPL 2004»
14 years 1 months ago
Evaluating Fault Emulation on FPGA
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, K...