41 search results - page 5 / 9 » Sequential logic synthesis using symbolic bi-decomposition |
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
14 years 1 days ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
ICFP
2005
ACM
14 years 1 months ago
2005
ACM
Narrowing-driven partial evaluation is a powerful technique for the specialization of (first-order) functional and functional logic programs. However, although it gives good resu...
FPGA
2009
ACM
14 years 2 months ago
2009
ACM
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is cap...
TAP
2009
Springer
14 years 2 months ago
2009
Springer
Abstract. This paper extends dynamic symbolic execution to distributed and concurrent systems. Dynamic symbolic execution can be used in software testing to systematically identify...