38 search results - page 5 / 8 » Serial-link bus: a low-power on-chip bus architecture |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
In this paper, we propose an adaptive low-power bus encoding algorithm based on weighted code mapping (WCM) and the delayed bus technique. The WCM algorithm transforms an original...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
ISQED
2008
IEEE
14 years 1 months ago
2008
IEEE
Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This i...
ISLPED
2000
ACM
13 years 11 months ago
2000
ACM
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Variou...
FDL
2003
IEEE
14 years 21 days ago
2003
IEEE
With System on Chip low power constraints becoming increasingly important, emphasis is moving to architectural level, optimum memory organisation and system run time management. T...