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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 18 days ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
HPDC
2002
IEEE
14 years 14 days ago
Multigrain Parallelism for Eigenvalue Computations on Networks of Clusters
Clusters of workstations have become a cost-effective means of performing scientific computations. However, large network latencies, resource sharing, and heterogeneity found in ...
James R. McCombs, Andreas Stathopoulos
ICCAD
1999
IEEE
86views Hardware» more  ICCAD 1999»
13 years 11 months ago
A framework for testing core-based systems-on-a-chip
Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions....
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jh...
ICS
2010
Tsinghua U.
13 years 11 months ago
Memory Consistency Conditions for Self-Assembly Programming
: Perhaps the two most significant theoretical questions about the programming of self-assembling agents are: (1) necessary and sufficient conditions to produce a unique terminal a...
Aaron Sterling
CASES
2006
ACM
13 years 11 months ago
High-performance packet classification algorithm for many-core and multithreaded network processor
Packet classification is crucial for the Internet to provide more value-added services and guaranteed quality of service. Besides hardware-based solutions, many software-based cla...
Duo Liu, Bei Hua, Xianghui Hu, Xinan Tang