109 search results - page 11 / 22 » Simplifying Instruction Issue Logic in Superscalar Processor... |
IEEEPACT
2005
IEEE
14 years 1 months ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
EMSOFT
2001
Springer
14 years 17 min ago
2001
Springer
Abstract. Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting...
PACS
2004
Springer
14 years 26 days ago
2004
Springer
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
ISSS
2002
IEEE
14 years 12 days ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...