109 search results - page 15 / 22 » Simplifying Instruction Issue Logic in Superscalar Processor... |
AES
2000
Springer
13 years 12 months ago
2000
Springer
We compare the five candidates for the Advanced Encryption Standard based on their performance on the Alpha 21264, a 64-bit superscalar processor. There are several new features o...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
PDPTA
2003
13 years 9 months ago
2003
The performance of the data memory hierarchy is extremely important in current and near future high performance superscalar microprocessors. To address the memory gap, computer de...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...