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SASP
2009
IEEE
291views Hardware» more  SASP 2009»
14 years 3 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
IEEEPACT
2009
IEEE
14 years 3 months ago
Quantifying the Potential of Program Analysis Peripherals
Abstract—As programmers are asked to manage more complicated parallel machines, it is likely that they will become increasingly dependent on tools such as multi-threaded data rac...
Mohit Tiwari, Shashidhar Mysore, Timothy Sherwood
IROS
2009
IEEE
150views Robotics» more  IROS 2009»
14 years 3 months ago
AWE: A robotic wall and reconfigurable desk supporting working life in a digital society
—“AWE” is a programmable “Animated Work Environment” supporting everyday human activities, at home, work and school, in an increasingly digital society. AWE features a no...
Keith Evan Green, Ian D. Walker, Leo J. Gugerty, J...
ARCS
2009
Springer
14 years 3 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
FCCM
2008
IEEE
212views VLSI» more  FCCM 2008»
14 years 2 months ago
Map-reduce as a Programming Model for Custom Computing Machines
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...