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» Simulation based deadlock analysis for system level designs
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ATS
2010
IEEE
229views Hardware» more  ATS 2010»
13 years 7 months ago
Variation-Aware Fault Modeling
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
Fabian Hopsch, Bernd Becker, Sybille Hellebrand, I...
ATAL
2005
Springer
14 years 2 months ago
Extending the recognition-primed decision model to support human-agent collaboration
There has been much research investigating team cognition, naturalistic decision making, and collaborative technology as it relates to real world, complex domains of practice. How...
Xiaocong Fan, Shuang Sun, Michael D. McNeese, John...
IPPS
2007
IEEE
14 years 3 months ago
Pseudo Trust: Zero-Knowledge Based Authentication in Anonymous Peer-to-Peer Protocols
Most of the current trust models in peer-to-peer (P2P) systems are identity based, which means that in order for one peer to trust another, it needs to know the other peer’s ide...
Li Lu, Jinsong Han, Lei Hu, Jinpeng Huai, Yunhao L...
CODES
2004
IEEE
14 years 18 days ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
13 years 17 days ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...