943 search results - page 52 / 189 » Simulation based deadlock analysis for system level designs |
STOC
1998
ACM
14 years 1 months ago
1998
ACM
In [6], Gallager introduces a family of codes based on sparse bipartite graphs, which he calls low-density parity-check codes. He suggests a natural decoding algorithm for these c...
ASYNC
2002
IEEE
14 years 1 months ago
2002
IEEE
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
TVLSI
2008
13 years 8 months ago
2008
With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validati...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
Logic Soft Errors caused by radiation are a major concern when working with circuits that need to operate in harsh environments, such as space or avionics applications, where soft ...
ISSS
2002
IEEE
14 years 1 months ago
2002
IEEE
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...