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» Simulation of High-Performance Memory Allocators
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ICC
2007
IEEE
246views Communications» more  ICC 2007»
14 years 5 months ago
AR-TP: An Adaptive and Responsive Transport Protocol for Wireless Mesh Networks
Abstract—Wireless meshing has been envisioned as the economically viable networking paradigm to build up broadband and large-scale wireless commodity networks. Several different ...
Vehbi Cagri Gungor, Pasquale Pace, Enrico Natalizi...
ICC
2007
IEEE
116views Communications» more  ICC 2007»
14 years 5 months ago
A New Cross Layer Approach to QoS-Aware Proportional Fairness Packet Scheduling in the Downlink of OFDM Wireless Systems
—OFDM systems are the major cellular platforms for supporting ubiquitous high performance mobile applications. However, there remain a number of research challenges to be tackled...
Zhen Kong, Jiangzhou Wang, Yu-Kwong Kwok
IWMM
2007
Springer
146views Hardware» more  IWMM 2007»
14 years 5 months ago
Allocation-phase aware thread scheduling policies to improve garbage collection performance
Past studies have shown that objects are created and then die in phases. Thus, one way to sustain good garbage collection efficiency is to have a large enough heap to allow many ...
Feng Xian, Witawas Srisa-an, Hong Jiang
IEEEPACT
2007
IEEE
14 years 5 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 3 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...