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» Simulation of High-Performance Memory Allocators
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MICRO
2008
IEEE
118views Hardware» more  MICRO 2008»
14 years 5 months ago
Notary: Hardware techniques to enhance signatures
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
Luke Yen, Stark C. Draper, Mark D. Hill
ISCA
1999
IEEE
110views Hardware» more  ISCA 1999»
14 years 3 months ago
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
JUCS
2000
120views more  JUCS 2000»
13 years 10 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
ICS
2007
Tsinghua U.
14 years 4 months ago
Cooperative cache partitioning for chip multiprocessors
This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a singl...
Jichuan Chang, Gurindar S. Sohi
HPCA
2009
IEEE
14 years 11 months ago
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
Mainak Chaudhuri