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» Simulation of High-Performance Memory Allocators
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IEEEPACT
2008
IEEE
14 years 5 months ago
Characterizing and modeling the behavior of context switch misses
One of the essential features in modern computer systems is context switching, which allows multiple threads of execution to time-share a limited number of processors. While very ...
Fang Liu, Fei Guo, Yan Solihin, Seongbeom Kim, Abd...
ICS
2005
Tsinghua U.
14 years 4 months ago
A performance-conserving approach for reducing peak power consumption in server systems
The combination of increasing component power consumption, a desire for denser systems, and the required performance growth in the face of technology-scaling issues are posing eno...
Wesley M. Felter, Karthick Rajamani, Tom W. Keller...
DAC
2004
ACM
14 years 11 months ago
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
Ashish Srivastava, Dennis Sylvester, David Blaauw
FMCAD
2006
Springer
14 years 2 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar
ASPLOS
2009
ACM
14 years 11 months ago
Phantom-BTB: a virtualized branch target buffer design
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
Ioana Burcea, Andreas Moshovos