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ICCAD
2001
IEEE
102views Hardware» more  ICCAD 2001»
14 years 4 months ago
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...
ISQED
2005
IEEE
106views Hardware» more  ISQED 2005»
14 years 1 months ago
Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE
The purpose of the paper is to introduce a new failure rate-based methodology for reliability simulation of deep submicron CMOS integrated circuits. Firstly, two of the state-of-t...
Xiaojun Li, Bing Huang, J. Qin, X. Zhang, Michael ...
FPL
2008
Springer
163views Hardware» more  FPL 2008»
13 years 9 months ago
Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system
We have constructed a FPGA-based "early neural circuit simulator" to model the first two stages of stimulus encoding and processing in the rat whisker system. Rats use t...
Brian Leung, Yan Pan, Chris Schroeder, Seda Ogrenc...
ASPDAC
2006
ACM
97views Hardware» more  ASPDAC 2006»
14 years 1 months ago
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices
We present a technique for the fast and accurate simulation of largescale VLSI interconnects with nonlinear devices, called SASIMI. The numerical efficiency of this technique is ...
Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkat...
DATE
2003
IEEE
105views Hardware» more  DATE 2003»
14 years 25 days ago
Approximation Approach for Timing Jitter Characterization in Circuit Simulators
A new computational concept of timing jitter is proposed that is suitable for exploitation in circuit simulators. It is based on the approximation of computed noise characteristic...
Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulya...