—We propose a compact model for small signal non quasi static analysis of long channel symmetric double gate MOSFET. The model is based on the EKV formalism and is valid in all r...
We present some novel hardware implementations of a stack. All designs are clockless, fast, and energy efficient, while occupying modest area. We implemented a 42-place stack chip...
Jo C. Ebergen, Daniel Finchelstein, Russell Kao, J...
Defects not described by conventional fault models are a challenge for state-of-the-art fault diagnosis techniques. The X-fault model has been introduced recently as a modeling te...
Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji ...
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
The virtual ant introduced by Langton [Physica D 22 (1986) 120] has an interesting behavior, which has been studied in several contexts. Here we give a construction to calculate a...