1304 search results - page 165 / 261 » Simulation of Soliton Circuits |
VLSID
2010
IEEE
14 years 25 days ago
2010
IEEE
—We propose a compact model for small signal non quasi static analysis of long channel symmetric double gate MOSFET. The model is based on the EKV formalism and is valid in all r...
ASYNC
2004
IEEE
14 years 21 days ago
2004
IEEE
We present some novel hardware implementations of a stack. All designs are clockless, fast, and energy efficient, while occupying modest area. We implemented a 42-place stack chip...
DDECS
2008
IEEE
13 years 10 months ago
2008
IEEE
Defects not described by conventional fault models are a challenge for state-of-the-art fault diagnosis techniques. The X-fault model has been introduced recently as a modeling te...
FPGA
2008
ACM
13 years 10 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
DAM
2002
13 years 8 months ago
2002
The virtual ant introduced by Langton [Physica D 22 (1986) 120] has an interesting behavior, which has been studied in several contexts. Here we give a construction to calculate a...