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PATMOS
2007
Springer
14 years 3 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
14 years 2 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
14 years 2 months ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
14 years 26 days ago
Node Mergers in the Presence of Don't Cares
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Vale...
EUROCRYPT
2007
Springer
14 years 22 days ago
An Efficient Protocol for Secure Two-Party Computation in the Presence of Malicious Adversaries
We show an efficient secure two-party protocol, based on Yao's construction, which provides security against malicious adversaries. Yao's original protocol is only secur...
Yehuda Lindell, Benny Pinkas