Sciweavers

1304 search results - page 212 / 261
» Simulation of Soliton Circuits
Sort
View
GLVLSI
2003
IEEE
144views VLSI» more  GLVLSI 2003»
14 years 2 months ago
A hybrid adiabatic content addressable memory for ultra low-power applications
This paper presents a hybrid adiabatic content addressable memory (CAM). The CAM uses an adiabatic switching technique to reduce the energy consumption in the match line while kee...
Aiyappan Natarajan, David Jasinski, Wayne Burleson...
ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
14 years 2 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin
ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
14 years 2 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
ISLPED
2003
ACM
129views Hardware» more  ISLPED 2003»
14 years 2 months ago
A critical analysis of application-adaptive multiple clock processors
Enabled by the continuous advancement in fabrication technology, present day synchronous microprocessors include more than 100 million transistors and have clock speeds well in ex...
Emil Talpes, Diana Marculescu
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
14 years 2 months ago
Closed form expressions for extending step delay and slew metrics to ramp inputs
: Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these...
Chandramouli V. Kashyap, Charles J. Alpert, Frank ...