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» Simulation of Soliton Circuits
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ICCD
2001
IEEE
154views Hardware» more  ICCD 2001»
14 years 5 months ago
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the...
Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
ICCAD
2005
IEEE
105views Hardware» more  ICCAD 2005»
14 years 5 months ago
Response shaper: a novel technique to enhance unknown tolerance for output response compaction
The presence of unknown values in the simulation result is a key barrier to effective output response compaction in practice. This paper proposes a simple circuit module, called a...
Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Cha...
ICCAD
2005
IEEE
120views Hardware» more  ICCAD 2005»
14 years 5 months ago
Practical techniques to reduce skew and its variations in buffered clock networks
Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variation...
Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, P...
ICCAD
2003
IEEE
190views Hardware» more  ICCAD 2003»
14 years 5 months ago
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
ICCAD
2002
IEEE
143views Hardware» more  ICCAD 2002»
14 years 5 months ago
A Markov chain sequence generator for power macromodeling
In macromodeling-based power estimation, circuit macromodels are created from simulations of synthetic input vector sequences. Fast generation of these sequences with all possible...
Xun Liu, Marios C. Papaefthymiou