Sciweavers

1304 search results - page 5 / 261
» Simulation of Soliton Circuits
Sort
View
DATE
1999
IEEE
112views Hardware» more  DATE 1999»
13 years 11 months ago
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
Markus Bühler, Matthias Papesch, K. Kapp, Utz...
DAC
1995
ACM
13 years 11 months ago
Automatic Clock Abstraction from Sequential Circuits
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
Samir Jain, Randal E. Bryant, Alok Jain
CCE
2005
13 years 7 months ago
Numerical simulation of stochastic gene circuits
Armed with increasingly fast supercomputers and greater knowledge of the molecular mechanisms of gene expression, it is now practical to numerically simulate complex networks of r...
Howard Salis, Yiannis N. Kaznessis
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
13 years 12 months ago
Parametric Fault Simulation and Test Vector Generation
Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This...
Khaled Saab, Naim Ben Hamida, Bozena Kaminska
VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
14 years 7 months ago
Multiple Faults: Modeling, Simulation and Test
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Salu...