22 search results - page 4 / 5 » Simulation points for SPEC CPU 2006 |
JEC
2006
13 years 7 months ago
2006
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
—This paper introduces the microarchitecture and logical implementation of SMT (Simultaneous Multithreading) improvement of Godson-2 processor which is a 64-bit, four-issue, out-...
ISCA
2010
IEEE
14 years 13 days ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
Current taint checking architectures monitor tainted data usage mainly with control transfer instructions. An alarm is raised once the program counter becomes tainted. However, su...
ASPLOS
2006
ACM
13 years 11 months ago
2006
ACM
Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size desig...