† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
We address the problem of checking the routability of segmented channels using satisfiability. The segmented channel routing problem arises in the context of row-based field progr...
William N. N. Hung, Xiaoyu Song, Alan J. Coppola, ...
The increasing clock frequencies in high-end industrial circuits bring new routing challenges that can not be handled by traditional algorithms. An important design automation pro...
-- Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the final result, often by neg...
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...