20 search results - page 3 / 4 » Simultaneous Gate Sizing and Fanout Optimization |
ISLPED
2003
ACM
14 years 23 days ago
2003
ACM
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
ISLPED
1995
ACM
13 years 11 months ago
1995
ACM
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...