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» Sizing Rules for Bipolar Analog Circuit Design
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JETC
2008
127views more  JETC 2008»
13 years 6 months ago
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
Yong Zhan, Sachin S. Sapatnekar
ICCAD
2001
IEEE
103views Hardware» more  ICCAD 2001»
14 years 4 months ago
Interconnect Resource-Aware Placement for Hierarchical FPGAs
In this paper, we utilize Rent’s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design c...
Amit Singh, Ganapathy Parthasarathy, Malgorzata Ma...
ISCAS
2002
IEEE
153views Hardware» more  ISCAS 2002»
14 years 14 days ago
Biological learning modeled in an adaptive floating-gate system
We have implemented an aspect of learning and memory in the nervous system using analog electronics. Using a simple synaptic circuit we realize networks with Hebbian type adaptati...
Christal Gordon, Paul E. Hasler
ISQED
2007
IEEE
104views Hardware» more  ISQED 2007»
14 years 1 months ago
System Level Estimation of Interconnect Length in the Presence of IP Blocks
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...
Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh
ASPDAC
2004
ACM
130views Hardware» more  ASPDAC 2004»
14 years 29 days ago
Automatic process migration of datapath hard IP libraries
— While essential for high-performance circuit design, the custom nature of datapath components confines their use in only a few microprocessor companies. The reusability of dat...
Fang Fang, Jianwen Zhu