719 search results - page 23 / 144 » Sizing router buffers |
118
Voted
VLSID
2002
IEEE
16 years 4 months ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
101
Voted
ENTCS
2008
15 years 3 months ago
2008
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...
133
Voted
IWQOS
2001
Springer
15 years 8 months ago
2001
Springer
A novel algorithm for buffer management and packet scheduling is presented for providing loss and delay differentiation for traffic classes at a network router. The algorithm, cal...
146
Voted
AINA
2004
IEEE
15 years 7 months ago
2004
IEEE
Prior survey of RED algorithm deployment on multiqueue system with shared buffer was unfair and sensitive to congestion level by statically setting the parameters. In this paper, ...
126
Voted
ISPD
1999
ACM
15 years 8 months ago
1999
ACM
Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer ins...