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ISLPED
2007
ACM
92views Hardware» more  ISLPED 2007»
13 years 10 months ago
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
INFOCOM
2010
IEEE
13 years 7 months ago
Optimal Linear Network Coding Design for Secure Unicast with Multiple Streams
—Linear network coding is a promising technology that can maximize the throughput capacity of communication network. Despite this salient feature, there are still many challenges...
Jin Wang, Jianping Wang, Kejie Lu, Bin Xiao, Naiji...
VLSID
2002
IEEE
94views VLSI» more  VLSID 2002»
14 years 9 months ago
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like data path alignment, I/O connec...
Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
ICCAD
2005
IEEE
104views Hardware» more  ICCAD 2005»
14 years 6 months ago
Design of DNA origami
— The generation of arbitrary patterns and shapes at very small scales is at the heart of our effort to miniaturize circuits and is fundamental to the development of nanotechnolo...
Paul W. K. Rothemund
INFOCOM
2009
IEEE
14 years 3 months ago
Routing Metric Designs for Greedy, Face and Combined-Greedy-Face Routing
Abstract—Different geographic routing protocols have different requirements on routing metric designs to ensure proper operation. Combining a wrong type of routing metric with a ...
Yujun Li, Yaling Yang, Xianliang Lu