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DATE
2006
IEEE
89views Hardware» more  DATE 2006»
14 years 4 months ago
Automatic insertion of low power annotations in RTL for pipelined microprocessors
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt ...
CHES
2003
Springer
247views Cryptology» more  CHES 2003»
14 years 4 months ago
Very Compact FPGA Implementation of the AES Algorithm
Abstract. In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key ...
Pawel Chodowiec, Kris Gaj
FPL
2008
Springer
91views Hardware» more  FPL 2008»
14 years 8 days ago
Power efficient DSP datapath configuration methodology for FPGA
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within ...
Stephen McKeown, Roger Woods, John McAllister
BMCBI
2010
218views more  BMCBI 2010»
13 years 8 months ago
A hybrid blob-slice model for accurate and efficient detection of fluorescence labeled nuclei in 3D
Background: To exploit the flood of data from advances in high throughput imaging of optically sectioned nuclei, image analysis methods need to correctly detect thousands of nucle...
Anthony Santella, Zhuo Du, Sonja Nowotschin, Anna-...
DAC
2006
ACM
14 years 4 months ago
Practical aspects of reliability analysis for IC designs
T. Pompl, C. Schlünder, M. Hommel, H. Nielen,...