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DATE
1998
IEEE
98views Hardware» more  DATE 1998»
14 years 2 months ago
AFTA: A Formal Delay Model for Functional Timing Analysis
Despite its importance, we find that a rigorous theoretical foundation for performing timing analysis has been lacking so far. As a result, we have initiated a research project th...
V. Chandramouli, Jesse Whittemore, Karem A. Sakall...
CDC
2009
IEEE
148views Control Systems» more  CDC 2009»
14 years 2 months ago
An adaptive artificial potential function approach for geometric sensing
In this paper, a novel artificial potential function is proposed for planning the path of a robotic sensor in a partially observed environment containing multiple obstacles and mul...
Guoxian Zhang, Silvia Ferrari
DATE
2004
IEEE
148views Hardware» more  DATE 2004»
14 years 1 months ago
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions
This paper presents a new decision diagram (DD), called MODD, for multiple output binary and multiple-valued functions. This DD is canonic and can be made minimal with respect to ...
Abusaleh M. Jabir, Dhiraj K. Pradhan
FPGA
2000
ACM
145views FPGA» more  FPGA 2000»
14 years 1 months ago
A C compiler for a processor with a reconfigurable functional unit
This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that c...
Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerje...
MPC
2000
Springer
105views Mathematics» more  MPC 2000»
14 years 1 months ago
The Universal Resolving Algorithm: Inverse Computation in a Functional Language
Abstract. We present an algorithm for inverse computation in a rstorder functional language based on the notion of a perfect process tree. The Universal Resolving Algorithm (URA) i...
Sergei M. Abramov, Robert Glück