81 search results - page 9 / 17 » Smaller explicit superconcentrators |
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
SMA
2005
ACM
14 years 1 months ago
2005
ACM
Numerous simplification methods have been proposed for speeding up engineering analysis/ simulation. A recently proposed medial axis reduction is one such method, that is particul...
SAMOS
2004
Springer
14 years 25 days ago
2004
Springer
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...