205 search results - page 11 / 41 » SoC Design and Test Considerations |
VLSID
2005
IEEE
14 years 9 days ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
DATE
2003
IEEE
14 years 13 hour ago
2003
IEEE
ng precision of abstract SystemC models using the SystemC Verification Standard Franco Carbognani1 , Christopher K. Lennard2 , C. Norris Ip3 , Allan Cochrane2 , Paul Bates2 1 Caden...
FDL
2005
IEEE
14 years 10 days ago
2005
IEEE
Verification and validation are key issues for today's SoC design projects. This paper presents the implementation of a SystemC based environment for transaction-based verifi...
DATE
2005
IEEE
14 years 10 days ago
2005
IEEE
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write o...