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» SoC Design and Test Considerations
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VTS
2007
IEEE
103views Hardware» more  VTS 2007»
14 years 29 days ago
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester
In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...
Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
DAC
2001
ACM
14 years 7 months ago
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive ...
Li Chen, Xiaoliang Bai, Sujit Dey
ET
2002
115views more  ET 2002»
13 years 6 months ago
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
ITC
1989
IEEE
82views Hardware» more  ITC 1989»
13 years 10 months ago
CMOS IC Stuck-Open Fault Electrical Effects and Design Considerations
- The electrical effects of CMOS IC physical defects that caused stuck-openfaults are evaluated, including their voltage levels, quiescent power supply current (IDDQ), transient re...
Jerry M. Soden, R. Keith Treece, Michael R. Taylor...
ISQED
2009
IEEE
137views Hardware» more  ISQED 2009»
14 years 1 months ago
Active decap design considerations for optimal supply noise reduction
Active decoupling capacitors (decaps) are more effective than passive decaps at reducing local IR-drop problems in the power distribution network. In the basic active decap, two p...
Xiongfei Meng, Resve A. Saleh