50 search results - page 5 / 10 » Soft Scheduling in High Level Synthesis |
TVLSI
2008
13 years 9 months ago
2008
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
ISSS
2000
IEEE
14 years 2 months ago
2000
IEEE
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
VLSID
2009
IEEE
14 years 10 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
ICCAD
2001
IEEE
14 years 6 months ago
2001
IEEE
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...