Sciweavers

155 search results - page 17 / 31
» Soft delay error analysis in logic circuits
Sort
View
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
14 years 29 days ago
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M....
ISQED
2003
IEEE
102views Hardware» more  ISQED 2003»
14 years 29 days ago
Modeling Crosstalk Induced Delay
The amplitude of coupled noise is often used in estimating the crosstalk effect. Coupling noise-induced delay measures the impact of crosstalk on circuit performance. Efficient c...
Chung-Kuan Tsai, Malgorzata Marek-Sadowska
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
14 years 2 months ago
Statistical fault injection: Quantified error and confidence
— Fault injection has become a very classical method to determine the dependability of an integrated system with respect to soft errors. Due to the huge number of possible error ...
Régis Leveugle, A. Calvez, Paolo Maistri, P...
DAC
2008
ACM
14 years 8 months ago
Parameterized timing analysis with general delay models and arbitrary variation sources
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
Khaled R. Heloue, Farid N. Najm
ISQED
2005
IEEE
133views Hardware» more  ISQED 2005»
14 years 1 months ago
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...
Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao ...