155 search results - page 30 / 31 » Soft delay error analysis in logic circuits |
DATE
2010
IEEE
14 years 23 days ago
2010
IEEE
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
VTS
2002
IEEE
14 years 17 days ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
JLP
2008
13 years 7 months ago
2008
Asynchronous method calls have been proposed to better integrate object orientation with distribution. In the Creol language, asynchronous method calls are combined with so-called...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...