Register-transfer level estimation techniques for switching activity and power consumption

We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of glitching activity at various data path and control signals, which can lead to significant underestimation of switching activity. For data path blocks that operate on word-level data, we construct piecewiselinearmodels that capture the variation ofoutputglitching activity and powerconsumptionwith various word-levelparameterslike mean, standarddeviation, spatialand temporal correlations, andglitching activity at the block's inputs. For RTL blocks that operate on data that need not have an associated word-level value, we present accurate bit-level modeling techniques for glitching activity as well as power consumption. This allows us to perform accurate power estimation for control-flow intensive circuits, where most of the power consumed is dissipated in non-arithmetic components like multiplexers, register...

• Type: Conference
• Year: 1996
• Where: ICCAD
• Authors: Anand Raghunathan, Sujit Dey, Niraj K. Jha
• Keywords: Glitching, Hardware, ICCAD 1996, Power Consumption, Switching Activity