32 search results - page 5 / 7 » Soft-Error Tolerance Analysis and Optimization of Nanometer ... |
VLSID
2007
IEEE
14 years 2 months ago
2007
IEEE
As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
— With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efï¬...
ISQED
2007
IEEE
14 years 2 months ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— The impact of process variations increases as technology scales to nanometer region. Under large process variations, the path and arc/node criticality [18] provide effe...