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CODES
2006
IEEE
14 years 2 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
CODES
2009
IEEE
14 years 3 months ago
FRA: a flash-aware redundancy array of flash storage devices
Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as storage med...
Yangsup Lee, Sanghyuk Jung, Yong Ho Song
GECCO
2009
Springer
103views Optimization» more  GECCO 2009»
14 years 3 months ago
GAMA (genetic algorithm driven multi-agents)for e-commerce integrative negotiation
Software agents help automate a variety of tasks including those involved in buying and selling products over the internet. The need for handling complex highly configurable produ...
Magda Bahaa Eldin Fayek, Ihab A. Talkhan, Khalil S...
CODES
2005
IEEE
14 years 2 months ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
CODES
2003
IEEE
14 years 1 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...