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DFT
2007
IEEE
112views VLSI» more  DFT 2007»
15 years 10 months ago
Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model
During semiconductor manufacturing, particles undesirably depose on the surface of the wafer causing “open” and “short” defects to interconnects. In this paper, a third ty...
Rani S. Ghaida, Payman Zarkesh-Ha
156
Voted
CODES
2003
IEEE
15 years 9 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
DATE
2009
IEEE
130views Hardware» more  DATE 2009»
15 years 10 months ago
An accurate interconnect thermal model using equivalent transmission line circuit
Abstract—This paper presents an accurate interconnect thermal model for analyzing the temperature distribution of an on-chip interconnect wire. The model addresses the ambient te...
Baohua Wang, Pinaki Mazumder
120
Voted
ICSE
1999
IEEE-ACM
15 years 7 months ago
Using Off-the-Shelf Middleware to Implement Connectors in Distributed Software Architectures
Software architectures promote development focused on modular building blocks and their interconnections. Since architecture-level components often contain complex functionality, ...
Eric M. Dashofy, Nenad Medvidovic, Richard N. Tayl...
CODES
2007
IEEE
15 years 10 months ago
Embedded software development on top of transaction-level models
Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write o...
Wolfgang Klingauf, Robert Günzel, Christian S...