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MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
13 years 8 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
CODES
2002
IEEE
14 years 3 months ago
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
The aggressive evolution of the semiconductor industry — smaller process geometries, higher densities, and greater chip complexity — has provided design engineers the means to...
Mohamed Shalan, Vincent John Mooney III
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
14 years 2 months ago
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
HIPEAC
2005
Springer
14 years 3 months ago
Memory-Centric Security Architecture
Abstract. This paper presents a new security architecture for protecting software confidentiality and integrity. Different from the previous process-centric systems designed for ...
Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee
AICCSA
2006
IEEE
102views Hardware» more  AICCSA 2006»
14 years 2 months ago
An Experimental and Industrial Experience: Avoiding Denial of Service via Memory Profiling
Poor memory management leads to memory leaks, which cause significant performance degradation and failure of software. If ignored, such leaks can potentially cause security breach...
Saeed Abu-Nimeh, Suku Nair, Marco F. Marchetti