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ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
14 years 4 months ago
A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies
In this paper, we present a hardware solution to perform non cache-line aligned memory copies allowing the commonly used memcpy function to cope with word copies. The main purpose...
Filipa Duarte, Stephan Wong
IEEEINTERACT
2003
IEEE
14 years 3 months ago
Compiler Support for Dynamic Speculative Pre-Execution
Speculative pre-execution is a promising prefetching technique which uses an auxiliary assisting thread in addition to the main program flow. A prefetching thread (p-thread), whic...
Won Woo Ro, Jean-Luc Gaudiot
CODES
1998
IEEE
14 years 2 months ago
Software timing analysis using HW/SW cosimulation and instruction set simulator
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculate...
Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-V...
ENTCS
2007
114views more  ENTCS 2007»
13 years 10 months ago
Parametric Performance Contracts for Software Components with Concurrent Behaviour
Performance prediction methods for component-based software systems aim at supporting design decisions of software architects during early development stages. With the increased a...
Jens Happe, Heiko Koziolek, Ralf Reussner
SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
14 years 4 months ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...