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CODES
2008
IEEE
14 years 2 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
ISCA
2008
IEEE
134views Hardware» more  ISCA 2008»
14 years 1 months ago
Flexible Decoupled Transactional Memory Support
A high-concurrency transactional memory (TM) implementation needs to track concurrent accesses, buffer speculative updates, and manage conflicts. We present a system, FlexTM (FLE...
Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. ...
MICRO
2008
IEEE
103views Hardware» more  MICRO 2008»
14 years 1 months ago
Testudo: Heavyweight security analysis via statistical sampling
Heavyweight security analysis systems, such as taint analysis and dynamic type checking, are powerful technologies used to detect security vulnerabilities and software bugs. Tradi...
Joseph L. Greathouse, Ilya Wagner, David A. Ramos,...
IPPS
2007
IEEE
14 years 1 months ago
Design Alternatives for a High-Performance Self-Securing Ethernet Network Interface
This paper presents and evaluates a strategy for integrating the Snort network intrusion detection system into a high-performance programmable Ethernet network interface card (NIC...
Derek L. Schuff, Vijay S. Pai
ISPASS
2007
IEEE
14 years 1 months ago
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...
Matt T. Yourst