271 search results - page 35 / 55 » Software transactional memory for dynamic-sized data structu... |
ISCA
2010
IEEE
14 years 1 months ago
2010
IEEE
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
APSEC
1996
IEEE
14 years 23 days ago
1996
IEEE
This paper is concerned with the design and performance of the telephone directory enquiry system newly adopted in Hong Kong. This system maintains three million telephone records...
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
JCC
2008
13 years 8 months ago
2008
: For the new parallel implementation of electronic structure methods in ACES III (Lotrich et al., in preparation) the present state-of-the-art algorithms for the evaluation of ele...
ASPLOS
2010
ACM
13 years 12 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...