354 search results - page 53 / 71 » Sorting networks on FPGAs |
FPGA
2003
ACM
14 years 3 months ago
2003
ACM
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
FPL
2003
Springer
14 years 3 months ago
2003
Springer
Abstract. This paper explores using information about program branch probabilities to optimise reconfigurable designs. The basic premise is to promote utilization by dedicating mo...
FPGA
2001
ACM
14 years 2 months ago
2001
ACM
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
MSE
1999
IEEE
14 years 2 months ago
1999
IEEE
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
DAC
2008
ACM
13 years 11 months ago
2008
ACM
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation i...