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IESS
2007
Springer
92views Hardware» more  IESS 2007»
14 years 1 months ago
An Interactive Model Re-Coder for Efficient SoC Specification
To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation...
Pramod Chandraiah, Rainer Dömer
RTCSA
2005
IEEE
14 years 29 days ago
An On-Chip Garbage Collection Coprocessor for Embedded Real-Time Systems
Garbage collection considerably increases programmer productivity and software quality. However, it is difficult to implement garbage collection both efficiently and suitably fo...
Matthias Meyer
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
13 years 11 months ago
Analysis and optimization of fault-tolerant embedded systems with hardened processors
1 In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques...
Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru ...
TODAES
2008
158views more  TODAES 2008»
13 years 7 months ago
Designing secure systems on reconfigurable hardware
The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integ...
Ted Huffmire, Brett Brotherton, Nick Callegari, Jo...
CHI
2011
ACM
12 years 11 months ago
Dealing with death in design: developing systems for the bereaved
Increasingly, systems are being developed and used in ways that involve end of life issues such as death, dying, and bereavement. Yet design considerations and guidelines for tech...
Michael Massimi, Ronald M. Baecker