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» Speculative Parallel Threading Architecture and Compilation
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IPPS
1994
IEEE
13 years 11 months ago
Building Multithreaded Architectures with Off-the-Shelf Microprocessors
Present-day parallel computers often face the problems of large software Overheadsfor process switching and interprocessor communication. These problems are addressed by the Multi...
Herbert H. J. Hum, Kevin B. Theobald, Guang R. Gao
PDP
2002
IEEE
14 years 19 days ago
The CDAG: A Data Structure for Automatic Parallelization for a Multithreaded Architecture
Despite the explosive new interest in Distributed Computing, bringing software — particularly legacy software — to parallel platforms remains a daunting task. The Self Distrib...
Bernd Klauer, Frank Eschmann, Ronald Moore, Klaus ...
SIGPLAN
2008
13 years 7 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
13 years 7 months ago
Speculative Dynamic Vectorization
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
Alex Pajuelo, Antonio González, Mateo Valer...
HPCA
2008
IEEE
14 years 2 months ago
Speculative instruction validation for performance-reliability trade-off
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal